Synthetic z80asm opcodes

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pjshumphreys
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Synthetic z80asm opcodes

Post by pjshumphreys »

Hey Everyone,

I've recently found out that z80asm will under some circumstances generate 'synthetic' instructions than those specified in the source in order to compose an equivalent for instructions not supported for a target cpu. For instance, on the 8080 relative jump instructions are not available, so if a jr instruction is in a source file to be assembled for an 8080 then z80asm will instead silently substitute a jp instruction.

I'm not particularly keen on this behaviour for my own projects. Is there some existing means to make z80asm produce an invalid instruction error in such circumstances?

I see the available opcodes are listed in https://raw.githubusercontent.com/z88dk ... pcodes.txt.

If I were to create something like a "8080_strict" cpu type that doesn't have the synthetic jr opcodes would that work? would folks consider that something along those lines should be present by default?

Also, is there anything on the wiki I could be pointed to that documents this behaviour?
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feilipu
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Re: Synthetic z80asm opcodes

Post by feilipu »

I've recently found out that z80asm will under some circumstances generate 'synthetic' instructions than those specified in the source in order to compose an equivalent for instructions not supported for a target cpu. For instance, on the 8080 relative jump instructions are not available, so if a jr instruction is in a source file to be assembled for an 8080 then z80asm will instead silently substitute a jp instruction.
Just for context, I've copied my comments from the (unrelated) PR over here.
It is worth noting that z88dk-z80asm has implemented many useful synthetic translations from mnemonic to machine specific opcodes.

So ex de,hl and jr nn are available everywhere, as are ld (de+),a or ld hl,de for example. If a synthetic instruction can be provided, with no side effects, then it is usually available. And this makes writing "common" code much cleaner. Avoids lots of conditional assembly, which clouds logic and program flow.

So the author's question becomes do I want a jp here because it is faster? Otherwise can I use jr without concern and let z80asm decide when I give it a machine type to assemble to.

But it is easy to forget there's no magic and no common synthetic jr M,nn instruction, for example, because the gbz80 can't do it. So it does limit choice in some ways.

The good news is that z80asm will always do what you ask. It only provides synthetic alternatives if you're asking the "wrong" thing for the machine type you told it to assemble to.

Synthetics came before z80asm could do macro assembly. And since now it does support macros, you can choose your own poison. 😊
The alternatives (in some cases synthetic) also help keep z80asm very agnostic, as it consumes both INTEL and ZILOG mnemonics as well as extensions for z180, z80n, and Rabbit.

The onus is on the author to know either their machine, or know that they're writing once for multiple machines and are asking z80asm to do the grunt translation.

I don't know. Perhaps there is also a use for a "strict" or "pedantic" assemble option?
pjshumphreys
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Re: Synthetic z80asm opcodes

Post by pjshumphreys »

I think both the existing synthetic behaviour and a hypothetical "pedantic" behaviour would have their uses, but a pedantic mode is not something I need right now. I just found the synthetic behaviour surprising.

Also, is there a case for a synthetic "ld (nn), hl" instruction for gbz80? the lack of that seems to have tripped us both up in recent days.
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feilipu
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Re: Synthetic z80asm opcodes

Post by feilipu »

Also, is there a case for a synthetic "ld (nn), hl" instruction for gbz80?
I think that could be challenging, but I'm no judge.

Paulo was only been adding very simple translations that are without any side effect (on both registers or flags). Though, there are a few that do use the A register, or call additional helper functions, but in the main they are simple and transparent translations. And now that z80asm supports macros, I think he'd also be pointing in that direction too.

I don't think that a ld (nn),hl instruction emulation could be written any better than you had already done. It isn't simple to emulate.

Two mnemonics that are useful for gbz80 are the ex de,hl and ex sp,(hl). The opcode generated for gbz80 ex de,hl is: E5 D5 E1 D1

Unfortunately the ex sp,(hl) function has to be done with a helper. The opcode generated for gbz80 is: CD @__z80asm__ex_sp_hl
So the helper is super slow, and it is best to avoid it if at all possible.
pjshumphreys
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Re: Synthetic z80asm opcodes

Post by pjshumphreys »

I don't think that a ld (nn),hl instruction emulation could be written any better than you had already done. It isn't simple to emulate.
Very well. I just thought it was worth asking.

So is there anything which indicates what should be made as a synthetic opcode? Limited to something like 5 bytes or so? Or perhaps it was something that was done for simplicities sake before macro support was implemented?
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feilipu
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Re: Synthetic z80asm opcodes

Post by feilipu »

So is there anything which indicates what should be made as a synthetic opcode? Limited to something like 5 bytes or so?
Key things are: helps to "even out" capabilities across the different INTEL/ZILOG variants, to make support easier. And to have no side effects different to the original opcode. And yes, 4 or 5 bytes seems to be about the limit for what has been acceptable.

Initially I think (guess) there was a library of code written to do the work here, and the capability arose from needing to call functions from that.
Or perhaps it was something that was done for simplicities sake before macro support was implemented?
I think that's a fair assumption ;)
pjshumphreys
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Re: Synthetic z80asm opcodes

Post by pjshumphreys »

fair enough :)
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